SI7530DP-T1-GE3;中文规格书,Datasheet资料

Vishay Siliconix

N- and P-Channel 60-V (D-S) MOSFET

PRODUCT SUMMARY

VDS (V)

N-Ch

60

RDS(on) (Ω)0.075 at VGS = 10 V 0.100 at VGS = 4.5 V 0.064 at VGS = - 10 V 0.080 at VGS = - 4.5 V

ID (A)4.64.0- 5.0- 4.5

Qg (Typ.)12 nC

FEATURES

•Halogen-free According to IEC 61249-2-21

Available

•TrenchFET® Power MOSFET

•New Low Thermal Resistance PowerPAK®

Package with Low 1.07 mm Profile •100 % Rg Tested

P-Ch- 6047

PowerP AK SO-8 S1 D15.15 mm G1 S26.15 mm 12S2 34D1 G2 G2G187D1 D2 65D2 Bottom ViewOrdering Information:Si7530DP-T1-E3 (Lead (Pb)-free)Si7530DP-T1-GE3 (Lead (Pb)-free and Halogen-free)S1N-Channel MOSFETD2P-Channel MOSFETABSOLUTE MAXIMUM RATINGS TA = 25 °C, unless otherwise noted

N-Channel P-ChannelParameter Symbol Steady Steady 10 s10 s

VDS60- 60Drain-Source Voltage

VGS± 20Gate-Source Voltage

TA = 25°C4.63.0- 5.0- 3.2

IDContinuous Drain Current (TJ = 150 °C)a

TA = 70°C3.62.4- 4.0- 2.6

IDM15- 25Pulsed Drain Current

IS2.71.2- 2.9- 1.2Continuous Source Current (Diode Conduction)a

IAS15- 22Single Pulse Avalanche Current

L = 0.1 mH

EAS1124.2Single Pulse Repetitive Avalanche Energyb

TA = 25°C3.31.43.51.5

PDMaximum Power Dissipationa

TA = 70°C2.10.92.20.94

TJ, Tstg- 55 to 150Operating Junction and Storage Temperature Range

260Soldering Recommendations (Peak Temperature)c, d

Unit V

A

mJW°C

THERMAL RESISTANCE RATINGS

N-Channel P-ChannelParameter Symbol TypicalMaximumTypicalMaximumt ≤ 10 s29382736RthJAMaximum Junction-to-Ambienta

Steady State60856085RthJC4.05.23.34.3Maximum Junction-to-Case (Drain)Steady StateUnit °C/W

Notes:

a.Surface Mounted on 1” x 1” FR4 board. b.Duty Cycle ≤ 1 %.

c.See Solder Profile (www.vishay.com/ppg?73257). The PowerPAK SO-8 is a leadless package. The end of the lead terminal is exposed copper(not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is notrequired to ensure adequate bottom side solder interconnection.

d.Rework Conditions: manual soldering with a soldering iron is not recommended for leadless components. Document Number: 73249S09-0223-Rev. D, 09-Feb-09

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Si7530DP

Vishay Siliconix

SPECIFICATIONS TJ = 25 °C, unless otherwise noted

Parameter Symbol Test ConditionsMin.Static

Gate Threshold VoltageGate-Body Leakage

VGS(th) IGSS

VDS = VGS, ID = 250 µA VDS = VGS, ID = - 250 µA VDS = 0 V, VGS = ± 20 V VDS = 60 V, VGS = 0 V

Zero Gate Voltage Drain Current

IDSS

VDS = - 60 V, VGS = 0 VVDS = 60 V, VGS = 0 V, TJ = 55°C VDS = - 60 V, VGS = 0 V, TJ = 55°C

On-State Drain Currenta

ID(on)

VDS ≥ 5 V, VGS = 10 V VDS ≤ - 5 V, VGS = - 10 V VGS = 10 V, ID = 4.6 A

Drain-Source On-State Resistancea

RDS(on)

VGS = - 10 V, ID = - 5.0 A VGS = 4.5 V, ID = 4.0 A VGS = - 4.5 V, ID = - 4.5 A

Forward TransconductanceaDiode Forward VoltageaDynamicb

Total Gate ChargeGate-Source ChargeGate-Drain ChargeGate ResistanceTurn-On Delay TimeRise Time

Turn-Off Delay TimeFall Time

Source-Drain Reverse Recovery TimeReverse Recovery Energy

Qg Qgs Qgd Rgtd(on) trtd(off) tftrrQrr

P-Channel

VDS = - 30 V, VGS = - 10 V, ID = - 5.0 A

f = 1.0 MHz

N-Channel

VDD = 30 V, RL = 30 Ω ID ≅ 1 A, VGEN = 10 V, Rg = 6 ΩP-Channel

VDD = - 30 V, RL = 30 Ω ID ≅ - 1 A, VGEN = - 10 V, Rg = 6 Ω

IF = 2.7 A, dI/dt = 100 A/µsIF = - 5 A, dI/dt = 100 A/µsIF = 2.7 A, dI/dt = 100 A/µsIF = - 5 A, dI/dt = 100 A/µs

N-Ch

N-Channel

VDS = 30 V, VGS = 10 V, ID = 15 A

P-ChN-ChP-ChN-ChP-ChN-ChP-ChN-ChP-ChN-ChP-ChN-ChP-ChN-ChP-ChN-ChP-ChN-ChP-Ch

0.63.5

122624.53.571.577889156573030403357

2.51115151515251002045608066115

pCnsΩ

2040

nC

gfs VSD

VDS = 15 V, ID = 4.6 A VDS = - 15 V, ID = - 5.0 A IS = 2.7 A, VGS = 0 V IS = - 2.9 A, VGS = 0 V

N-ChP-ChN-ChP-ChN-ChP-ChN-ChP-ChN-ChP-ChN-ChP-ChN-ChP-ChN-ChP-ChN-ChP-Ch

15- 25

0.0600.0510.0800.0646160.85- 0.85

1.2- 1.20.0750.0640.1000.080

SVΩ

1- 1

3- 3± 100± 1001- 15- 5

AµAVnA

Typ.

Max.

Unit Notes:

a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2 %.

b. Guaranteed by design, not subject to production testing.

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operationof the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximumrating conditions for extended periods may affect device reliability.

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Si7530DP N-CHANNEL TYPICAL CHARACTERISTICS 25°C, unless otherwise noted15VGS = 10 V thru 4 V12ID- Drain Current (A)ID- Drain Current (A)1215Vishay Siliconix9963 V36TC = 125 °C25 °C 3-55 °C2.53.03.54.04.50012345VDS- Drain-to-Source Voltage (V)00.00.51.01.52.0VGS - Gate-to-Source Voltage (V)Output Characteristics0.12800700RDS(on)- On-Resistance (Ω)0.10C - Capacitance (pF)VGS = 4.5 V0.08VGS = 10 V0.06600500400300Transfer CharacteristicsCiss0.04Coss2000.0210000369121504Crss0.008121620ID- Drain Current (A) VDS - Drain-to-Source Voltage (V)On-Resistance vs. Drain Current20VDS = 30 VID = 15 A16RDS(on)- On-Resistance(Normalized)1.81.61.41.21.00.8004812162024Qg- Total Gate Charge (nC)0.62.22.0VGS = 10 VID = 10 ACapacitanceVGS- Gate-to-Source Voltage (V)1284-50-250255075100125150TJ- Junction Temperature (°C)Gate ChargeOn-Resistance vs. Junction TemperatureDocument Number: 73249S09-0223-Rev. D, 09-Feb-09www.vishay.com

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Si7530DPVishay Siliconix40 N-CHANNEL TYPICAL CHARACTERISTICS 25°C, unless otherwise noted0.2000.175RDS(on)- On-Resistance (Ω)IS- Source Current (A)TJ = 150 °C100.1500.1250.1000.0750.0500.02510.00.0000.20.40.60.81.01.20246810VSD- Source-to-Drain Voltage (V)VGS- Gate-to-Source Voltage (V)ID = 4.6 ATJ = 25 °CSource-Drain Diode Forward Voltage0.60.4800.2VGS(th)(V)0.0- 0.2- 0.4- 0.620- 0.8- 1.0- 50ID = 250 µAPower (W)60100On-Resistance vs. Gate-to-Source VoltageTA = 25 °CSingle Pulse40- 25025507510012515000.0010.010.1Time (s)110TJ - Temperature (°C)Threshold Voltage100Limited by IDM10Limited byRDS(on)*10 µs 100 µs Single Pulse Power

ID - Drain Current (A)11 ms10 msID(on)LimitedTA = 25 °CSingle Pulse100 ms1 sBVDSS Limited10 s100 sDC1000.10.010.1110 - Drain-to-Source Voltage (V)VDS* VGS> minimum VGS at which RDS(on) is specifiedSafe Operating Area, Junction-to-Case

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Si7530DP

N-CHANNEL TYPICAL CHARACTERISTICS 25°C, unless otherwise noted

21Normalized Effective TransientThermal ImpedanceDuty Cycle = 0.5Vishay Siliconix

0.20.10.10.050.02Single Pulse0.0110-410-310-210-11Square Wave Pulse Duration (s)Notes:PDMt1t21. Duty Cycle, D =t1t22. Per Unit Base = RthJA = 60 °C/W3. TJM- TA = PDMZthJA(t)4. Surface Mounted10100600Normalized Thermal Transient Impedance, Junction-to-Ambient

21Normalized Effective TransientThermal ImpedanceDuty Cycle = 0.50.20.10.10.050.02Single Pulse0.0110-410-310-210-1Square Wave Pulse Duration (s)10100Normalized Thermal Transient Impedance, Junction-to-Case

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Si7530DPVishay Siliconix P-CHANNEL TYPICAL CHARACTERISTICS 25°C, unless otherwise noted30VGS = 10 V thru 5 V25ID- Drain Current (A)4 VID- Drain Current (A)253020201515103 V10TC = 125 °C25 °C-55 °C0.51.01.52.02.53.03.54.04.5550024681000.0 - Drain-to-Source Voltage (V)VDS - Gate-to-Source Voltage (V)VGSOutput Characteristics0.121800Transfer Characteristics0.10RDS(on)- On-Resistance (Ω)C - Capacitance (pF)1500Ciss0.08VGS = 4.5 VVGS = 10 V12000.069000.04600CossCrss01020304050600.023000.000510152025300ID - Drain Current (A)VDS- Drain-to-Source Voltage (V)On-Resistance vs. Drain Current20VDS = 30 VID = 5 ARDS(on) - On-Resistance(Normalized)2.22.01.81.61.41.21.00.80.6001020304050Qg- Total Gate Charge (nC)0.4- 50VGS = 10 VID = 5 ACapacitanceVGS- Gate-to-Source Voltage (V)161284- 250255075100125150TJ- Junction Temperature (°C)Gate ChargeOn-Resistance vs. Junction Temperaturewww.vishay.com6Document Number: 73249S09-0223-Rev. D, 09-Feb-09

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Si7530DP

P-CHANNEL TYPICAL CHARACTERISTICS 25°C, unless otherwise noted400.30Vishay Siliconix0.25IS - Source Current (A)TJ = 150 °C10RDS(on)- On-Resistance (Ω)ID = 5 A0.200.150.10TJ = 25 °C0.0510.00.000.20.40.60.81.01.20246810VSD - Source-to-Drain Voltage (V)VGS- Gate-to-Source Voltage (V)Source-Drain Diode Forward Voltage

1.00.80.6VGS(th)(V)0.40.20.0-0.2-0.4-5020Power (W)60ID = 250 µA 80100On-Resistance vs. Gate-to-Source Voltage

40-25025507510012515000.0010.010.1Time (s)110TJ- Temperature (°C)Threshold Voltage100Single Pulse Power, Junction-to-Ambient

10ID - Drain Current (A)Limited by RDS(on)*10 µs 100 µs 11 ms10 ms100 ms0.1TA = 25 °CSingle Pulse1 s10 s100 s, DC0.010.0010.1110100VDS- Drain-to-Source Voltage (V)* VGS>minimum VGS at which RDS(on)is specifiedSafe Operating Area

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Si7530DP

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21Normalized Effective TransientThermal ImpedanceDuty Cycle = 0.5

P-CHANNEL TYPICAL CHARACTERISTICS 25°C, unless otherwise noted

0.20.10.10.050.02Single Pulse0.0110-410-310-210-11Square Wave Pulse Duration (s)Notes:PDMt1t21. Duty Cycle, D =t1t22. Per Unit Base = RthJA = 52 °C/W3. TJM- TA = PDMZthJA(t)4. Surface Mounted10100600Normalized Thermal Transient Impedance, Junction-to-Ambient21Normalized Effective TransientThermal ImpedanceDuty Cycle = 0.50.20.10.10.050.02Single Pulse0.0110-410-310-2SquareWave Pulse Duration (s)10-11Normalized Thermal Transient Impedance, Junction-to-Case

Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for SiliconTechnology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, andreliability data, see www.vishay.com/ppg?73249.www.vishay.com8Document Number: 73249S09-0223-Rev. D, 09-Feb-09

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Package Information

Vishay Siliconix

PowerPAK® SO-8, (SINGLE/DUAL)

HWθM122D1D34L1E3θθE2E4KLD412D2D534bbL1D12K1D534DθA10.150 ± 0.008D2ZecDetail ZD3(2x)D42E1EABackside View of Single PadHKE2E4D2Notes1.Inch will govern.2Dimensions exclusive of mold gate burrs.3.Dimensions exclusive of mold flash and cutting burrs.E3Backside View of Dual PadMILLIMETERS

DIM.AA1bcDD1D2D3D4D5EE1E2E3 E4eKK1HLL1θWM

ECN: T10-0055-Rev. J, 15-Feb-10DWG: 5881

0.560.510.510.060°0.156.055.793.483.68MIN.0.970.000.330.235.054.803.561.32

NOM.1.04-0.410.285.154.903.761.500.57 TYP.3.98 TYP.6.155.893.663.780.75 TYP.1.27 BSC1.27 TYP.

-0.610.610.13-0.250.125 TYP.

-0.710.710.2012°0.36

0.0220.0200.0200.0020°0.006

6.255.993.843.91

0.2380.2280.1370.145

MAX.1.120.050.510.335.265.003.911.68

MIN.0.0380.0000.0130.0090.1990.1890.1400.052

INCHESNOM.0.041-0.0160.0110.2030.1930.1480.0590.0225 TYP.0.157 TYP.0.2420.2320.1440.1490.030 TYP.0.050 BSC0.050 TYP.

-0.0240.0240.005-0.0100.005 TYP.

-0.0280.0280.00812°0.0140.2460.2360.1510.154MAX.0.0440.0020.0200.0130.2070.1970.1540.066

Document Number: 71655Revison: 15-Feb-10

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AN821

Vishay Siliconix

PowerPAK® SO-8 Mounting and Thermal Considerations

Wharton McDaniel

MOSFETs for switching applications are now availablewith die on resistances around 1 mΩ and with thecapability to handle 85 A. While these die capabilitiesrepresent a major advance over what was availablejust a few years ago, it is important for power MOSFETpackaging technology to keep pace. It should be obvi-ous that degradation of a high performance die by thepackage is undesirable. PowerPAK is a new packagetechnology that addresses these issues. In this appli-cation note, PowerPAK’s construction is described.Following this mounting information is presentedincluding land patterns and soldering profiles for max-imum reliability. Finally, thermal and electrical perfor-mance is discussed.

THE PowerPAK PACKAGE

The PowerPAK package was developed around theSO-8 package (Figure 1). The PowerPAK SO-8 uti-lizes the same footprint and the same pin-outs as thestandard SO-8. This allows PowerPAK to be substi-tuted directly for a standard SO-8 package. Being aleadless package, PowerPAK SO-8 utilizes the entireSO-8 footprint, freeing space normally occupied by theleads, and thus allowing it to hold a larger die than astandard SO-8. In fact, this larger die is slightly largerthan a full sized DPAK die. The bottom of the die attachpad is exposed for the purpose of providing a direct,low resistance thermal path to the substrate the deviceis mounted on. Finally, the package height is lowerthan the standard SO-8, making it an excellent choicefor applications with space constraints.

PowerPAK SO-8 SINGLE MOUNTING

The PowerPAK single is simple to use. The pinarrangement (drain, source, gate pins) and the pindimensions are the same as standard SO-8 devices(see Figure 2). Therefore, the PowerPAK connectionpads match directly to those of the SO-8. The only dif-ference is the extended drain connection area. To takeimmediate advantage of the PowerPAK SO-8 singledevices, they can be mounted to existing SO-8 landpatterns.

Standard SO-8PowerPAK SO-8

Figure 2.

The minimum land pattern recommended to take fulladvantage of the PowerPAK thermal performance seeApplication Note 826, Recommended Minimum PadPatterns With Outline Drawing Access for Vishay Sili-conix MOSFETs. Click on the PowerPAK SO-8 singlein the index of this document.

In this figure, the drain land pattern is given to make fullcontact to the drain pad on the PowerPAK package.This land pattern can be extended to the left, right, andtop of the drawn pattern. This extension will serve toincrease the heat dissipation by decreasing the ther-mal resistance from the foot of the PowerPAK to thePC board and therefore to the ambient. Note thatincreasing the drain land area beyond a certain pointwill yield little decrease in foot-to-board and foot-to-ambient thermal resistance. Under specific conditionsof board configuration, copper weight and layer stack,experiments have found that more than about 0.25 to0.5 in2 of additional copper (in addition to the drainland) will yield little improvement in thermal perfor-mance.

Figure 1. PowerPAK 1212 Devices

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SI7530DP-T1-GE3