GD25Q64B_Rev11

FEATURES

◆ 64M-bit Serial Flash ◆Program/Erase Speed-8192K-byte -Page Program time: 0.7ms typical

-256 bytes per programmable page -Sector Erase time: 100ms typical-Block Erase time: 0.2/0.4s typical

◆Standard, Dual, Quad SPI -Chip Erase time: 30s typical-Standard SPI: SCLK, CS#, SI, SO, WP#, HOLD#

-Dual SPI: SCLK, CS#, IO0, IO1, WP#, HOLD# ◆Flexible Architecture-Quad SPI: SCLK, CS#, IO0, IO1, IO2, IO3 -Sector of 4K-byte-Block of 32/64k-byte

◆High Speed Clock Frequency

-120MHz for fast read with 30PF load ◆Low Power Consumption-Dual I/O Data transfer up to 240Mbits/s -20mA maximum active current-Quad I/O Data transfer up to 480Mbits/s -5uA maximum power down current◆Software/Hardware Write Protection ◆ Advanced security Features(1)-Write protect all/portion of memory via software -16-Bit Customer ID

-Enable/Disable protection with WP# Pin -4*256-Byte Security Registers With OTP Lock-Top or Bottom, Sector or Block selection◆Single Power Supply Voltage

◆Minimum 100,000 Program/Erase Cycles -Full voltage range:2.7~3.6VNote: 1.Please contact Gigadevice for details.GENERAL DESCRIPTION

The GD25Q64B (64M-bit) Serial flash supports the standard Serial Peripheral Interface (SPI), and supports the Dual/QuadSPI: Serial Clock, Chip Select, Serial Data I/O0 (SI), I/O1 (SO), I/O2 (WP#), and I/O3 (HOLD#). The Dual I/O data istransferred with speed of 240Mbits/s and the Quad I/O & Quad output data is transferred with speed of 480Mbits/s.CONNECTION DIAGRAM

CS# SOVSSVCC

HOLD#SCLKSI

8–LEAD SOP/DIPCS#SO

VSSVCCHOLD#SI

8–LEAD WSON

A B C D E F4321

24-BALL TFBGA

BLOCK DIAGRAM

MEMORY ORGANIZATION

UNIFORM BLOCK SECTOR ARCHITECTURE

DEVICE OPERATIONSPI ModeStandard SPI

The GD25Q64B features a serial peripheral interface on 4 signals bus: Serial Clock (SCLK), Chip Select (CS#), Serial Data

Input (SI) and Serial Data Output (SO). Both SPI bus mode 0 and 3 are supported. Input data is latched on the rising edge ofSCLK and data shifts out on the falling edge of SCLK.Dual SPI

The GD25Q64B supports Dual SPI operation when using the “Dual Output Fast Read” and “Dual I/O Fast Read” (3BH andBBH) commands. These commands allow data to be transferred to or from the device at two times the rate of the standardSPI. When using the Dual SPI command the SI and SO pins become bidirectional I/O pins: IO0 and IO1.Quad SPI

The GD25Q64B supports Quad SPI operation when using the “Quad Output Fast Read”,” Quad I/O Fast Read”, “Quad I/OWord Fast Read” (6BH, EBH, E7H) commands. These commands allow data to be transferred to or from the device at fourtimes the rate of the standard SPI. When using the Quad SPI command the SI and SO pins become bidirectional I/O pins: IO0and IO1, and WP# and HOLD# pins become IO2 and IO3. Quad SPI commands require the non-volatile Quad Enable bit(QE) in Status Register to be set.Hold

The HOLD# signal goes low to stop any serial communications with the device, but doesn’t stop the operation of write statusregister, programming, or erasing in progress.

The operation of HOLD, need CS# keep low, and starts on falling edge of the HOLD# signal, with SCLK signal being low (ifSCLK is not being low, HOLD operation will not start until SCLK being low). The HOLD condition ends on rising edge ofHOLD# signal with SCLK being low (If SCLK is not being low, HOLD operation will not end until SCLK being low).The SO is high impedance, both SI and SCLK don’t care during the HOLD operation, if CS# drives high during HOLDoperation, it will reset the internal logic of the device. To re-start communication with chip, the HOLD# must be at high andthen CS# must be at low.Figure1. Hold Condition

Data Protection

The GD25Q64B provide the following data protection methods:

◆Write Enable (WREN) command: The WREN command is set the Write Enable Latch bit (WEL). The WEL bit willreturn to reset by the following situation:-Power-Up

-Write Disable (WRDI)-Write Status Register (WRSR)-Page Program (PP)

-Sector Erase (SE) / Block Erase (BE) / Chip Erase (CE)

◆Software Protection Mode: The Block Protect (BP4, BP3, BP2, BP1, BP0) bits define the section of the memoryarray that can be read but not change.

◆Hardware Protection Mode: WP# going low to protected the BP0~BP4 bits and SRP0~1 bits.

◆Deep Power-Down Mode: In Deep Power-Down Mode, all commands are ignored except the Release from DeepPower-Down Mode command.

Table1.0 GD25Q64B Protected area size (CMP=0)

Table1.1 GD25Q64B Protected area size (CMP=1)

The status and control bits of the Status Register are as follows:WIP bit.

The Write In Progress (WIP) bit indicates whether the memory is busy in program/erase/write status register progress. WhenWIP bit sets to 1, means the device is busy in program/erase/write status register progress, when WIP bit sets 0, means thedevice is not in program/erase/write status register progress.WEL bit.

The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. When set to 1 the internal WriteEnable Latch is set, when set to 0 the internal Write Enable Latch is reset and no Write Status Register, Program or Erasecommand is accepted.BP4, BP3, BP2, BP1, BP0 bits.

The Block Protect (BP4, BP3, BP2, BP1, BP0) bits are non-volatile. They define the size of the area to be software protectedagainst Program and Erase commands. These bits are written with the Write Status Register (WRSR) command. When theBlock Protect (BP4, BP3, BP2, BP1, BP0) bits are set to 1, the relevant memory area (as defined in Table1).becomes

protected against Page Program (PP), Sector Erase (SE) and Block Erase (BE) commands. The Block Protect (BP4, BP3,BP2, BP1, BP0) bits can be written provided that the Hardware Protected mode has not been set. The Chip Erase (CE)command is executed, only if the Block Protect (BP2, BP1, BP0) bits are 0.SRP1, SRP0 bits.

The Status Register Protect (SRP1 and SRP0) bits are non-volatile Read/Write bits in the status register. The SRP bits

control the method of write protection: software protection, hardware protection, power supply lock-down or one timeprogrammable protection.

NOTE:

1. When SRP1, SRP0= (1, 0), a Power-Down, Power-Up cycle will change SRP1, SRP0 to (0, 0) state.QE bit.

The Quad Enable (QE) bit is a non-volatile Read/Write bit in the Status Register that allows Quad operation. When the QE bitis set to 0 (Default) the WP# pin and HOLD# pin are enable. When the QE pin is set to 1, the Quad IO2 and IO3 pins areenabled. (The QE bit should never be set to 1 during standard SPI or Dual SPI operation if the WP# or HOLD# pins are tieddirectly to the power supply or ground)LB bit.

The LB bit is a non-volatile One Time Program (OTP) bit in Status Register (S10) that provide the write protect control andstatus to the Security Registers. The default state of LB is 0, the security registers are unlocked. LB can be set to 1

individually using the Write Register instruction. LB is One Time Programmable, once it’s set to 1, the Security Registers willbecome read-only permanently.CMP bit

The CMP bit is a non-volatile Read/Write bit in the Status Register (S14). It is used in conjunction the BP4-BP0 bits toprovide more flexibility for the array protection. Please see the Status registers Memory Protection table for details. Thedefault setting is CMP=0.SUS bit

The SUS bit are read only bit in the status register (S15 ) that are set to 1 after executing an Erase/Program Suspend (75H)command. The SUS bit are cleared to 0 by Erase/Program Resume (7AH) command as well as a power-down, power-upcycle.

COMMANDS DESCRIPTION

All commands, addresses and data are shifted in and out of the device, beginning with the most significant bit on the firstrising edge of SCLK after CS# is driven low. Then, the one-byte command code must be shifted in to the device, mostsignificant bit first on SI, each bit being latched on the rising edges of SCLK.

See Table2, every command sequence starts with a one-byte command code. Depending on the command, this might befollowed by address bytes, or by data bytes, or by both or none. CS# must be driven high after the last bit of the commandsequence has been shifted in. For the command of Read, Fast Read, Read Status Register or Release from Deep Power-Down, and Read Device ID, the shifted-in command sequence is followed by a data-out sequence. CS# can be driven highafter any bit of the data-out sequence is being shifted out.

For the command of Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register, Write Enable, WriteDisable or Deep Power-Down command, CS# must be driven high exactly at a byte boundary, otherwise the command isrejected, and is not executed. That is CS# must driven high when the number of clock pulses after CS# being driven low isan exact multiple of eight. For Page Program, if at any time the input byte is not a full byte, nothing will happen and WEL willnot be reset.

1. Dual Output dataIO0 = (D6, D4, D2, D0)IO1 = (D7, D5, D3, D1)2. Dual Input Address

IO0 = A22, A20, A18, A16, A14, A12, A10, A8 A6, A4, A2, A0, M6, M4, M2, M0

IO1 = A23, A21, A19, A17, A15, A13, A11, A9 A7, A5, A3, A1, M7, M5, M3, M1 3. Quad Output DataIO0 = (D4, D0, …..)IO1 = (D5, D1, …..)IO2 = (D6, D2, …..)IO3 = (D7, D3,…..)4. Quad Input Address

IO0 = A20, A16, A12, A8, A4, A0, M4, M0

IO1 = A21, A17, A13, A9, A5, A1, M5, M1IO2 = A22, A18, A14, A10, A6, A2, M6, M2IO3 = A23, A19, A15, A11, A7, A3, M7, M35. Fast Read Quad I/O DataIO0 = (x, x, x, x, D4, D0,…)IO1 = (x, x, x, x, D5, D1,…)IO2 = (x, x, x, x, D6, D2,…)IO3 = (x, x, x, x, D7, D3,…)6. Fast Word Read Quad I/O DataIO0 = (x, x, D4, D0,…)IO1 = (x, x, D5, D1,…)IO2 = (x, x, D6, D2,…)IO3 = (x, x, D7, D3,…)

7. Fast Word Read Quad I/O Data: the lowest address bit must be 0.8. Security Registers Address:

Security Register: A23-A16=00000000b, A14-A10=0000b, A9-A0= Address;Table of ID Definitions:

Write Enable (WREN) (06H)

The Write Enable (WREN) command is for setting the Write Enable Latch (WEL) bit. The Write Enable Latch (WEL) bit mustbe set prior to every Page Program (PP), Sector Erase (SE), Block Erase (BE), Chip Erase (CE) and Write Status Register(WRSR) command. The Write Enable (WREN) command sequence: CS# goes low → sending the Write Enable command →CS# goes high.

Figure2. Write Enable Sequence Diagram

Write Disable (WRDI) (04H)

The Write Disable command is for resetting the Write Enable Latch (WEL) bit. The Write Disable command sequence: CS#goes low→Sending the Write Disable command →CS# goes high. The WEL bit is reset by following condition: Power-up andupon completion of the Write Status Register, Page Program, Sector Erase, Block Erase and Chip Erase commands.Figure3. Write Disable Sequence Diagram

Read Status Register (RDSR) (05H or 35H)

The Read Status Register (RDSR) command is for reading the Status Register. The Status Register may be read at any time,even while a Program, Erase or Write Status Register cycle is in progress. When one of these cycles is in progress, it isrecommended to check the Write In Progress (WIP) bit before sending a new command to the device. It is also possible toread the Status Register continuously. For command code “05H”, the SO will output Status Register bits S7~S0. Thecommand code “35H”, the SO will output Status Register bits S15~S8.Figure4. Read Status Register Sequence Diagram

Write Status Register (WRSR) (01H)

The Write Status Register (WRSR) command allows new values to be written to the Status Register. Before it can be

accepted, a Write Enable (WREN) command must previously have been executed. After the Write Enable (WREN) commandhas been decoded and executed, the device sets the Write Enable Latch (WEL).

The Write Status Register (WRSR) command has no effect on S15, S1 and S0 of the Status Register. CS# must be drivenhigh after the eighth or sixteen bit of the data byte has been latched in. If not, the Write Status Register (WRSR) command isnot executed. If CS# is driven high after eighth bit of the data byte, the CMP and QE and SRP1 bits will be cleared to 0. Assoon as CS# is driven high, the self-timed Write Status Register cycle (whose duration is t W) is initiated. While the WriteStatus Register cycle is in progress, the Status Register may still be read to check the value of the Write In Progress (WIP)bit. The Write In Progress (WIP) bit is 1 during the self-timed Write Status Register cycle, and is 0 when it is completed. Whenthe cycle is completed, the Write Enable Latch (WEL) is reset.

The Write Status Register (WRSR) command allows the user to change the values of the Block Protect (BP4, BP3, BP2,BP1, BP0) bits, to define the size of the area that is to be treated as read-only, as defined in Table1. The Write StatusRegister (WRSR) command also allows the user to set or reset the Status Register Protect (SRP1 and SRP0) bits in

accordance with the Write Protect (WP#) signal. The Status Register Protect (SRP1 and SRP0) bits and Write Protect (WP#)signal allow the device to be put in the Hardware Protected Mode. The Write Status Register (WRSR) command is notexecuted once the Hardware Protected Mode is entered.Figure5. Write Status Register Sequence Diagram

Read Data Bytes (READ) (03H)

The Read Data Bytes (READ) command is followed by a 3-byte address (A23-A0), each bit being latched-in during the risingedge of SCLK. Then the memory content, at that address, is shifted out on SO, each bit being shifted out, at a Max frequency

f R, during the falling edge of SCLK. The first byte addressed can be at any location. The address is automatically

incremented to the next higher address after each byte of data is shifted out. The whole memory can, therefore, be read witha single Read Data Bytes (READ) command. Any Read Data Bytes (READ) command, while an Erase, Program or Writecycle is in progress, is rejected without having any effects on the cycle that is in progress.Figure6. Read Data Bytes Sequence Diagram

Read Data Bytes At Higher Speed (Fast Read) (0BH)

The Read Data Bytes at Higher Speed (Fast Read) command is for quickly reading data out. It is followed by a 3-byte

address (A23-A0) and a dummy byte, each bit being latched-in during the rising edge of SCLK. Then the memory content, atthat address, is shifted out on SO, each bit being shifted out, at a Max frequency f C, during the falling edge of SCLK. The firstbyte addressed can be at any location. The address is automatically incremented to the next higher address after each byteof data is shifted out.

Figure7. Read Data Bytes at Higher Speed Sequence Diagram

Dual Output Fast Read (3BH)

The Dual Output Fast Read command is followed by 3-byte address (A23-A0) and a dummy byte, each bit being latched induring the rising edge of SCLK, then the memory contents are shifted out 2-bit per clock cycle from SI and SO. The commandsequence is shown in followed Figure8. The first byte addressed can be at any location. The address is automaticallyincremented to the next higher address after each byte of data is shifted out.Figure8. Dual Output Fast Read Sequence Diagram

Quad Output Fast Read (6BH)

The Quad Output Fast Read command is followed by 3-byte address (A23-A0) and a dummy byte, each bit being latched induring the rising edge of SCLK, then the memory contents are shifted out 4-bit per clock cycle from IO3, IO2, IO1 and IO0.The command sequence is shown in followed Figure9. The first byte addressed can be at any location. The address isautomatically incremented to the next higher address after each byte of data is shifted out.Figure9. Quad Output Fast Read Sequence Diagram

Dual I/O Fast Read (BBH)

The Dual I/O Fast Read command is similar to the Dual Output Fast Read command but with the capability to input the 3-byteaddress (A23-0) and a “Continuous Read Mode” byte 2-bit per clock by SI and SO, each bit being latched in during the risingedge of SCLK, then the memory contents are shifted out 2-bit per clock cycle from SI and SO. The command sequence isshown in followed Figure10. The first byte addressed can be at any location. The address is automatically incremented to thenext higher address after each byte of data is shifted out. To ensure optimum performance the High Performance Mode(HPM) command (A3H) must be executed once, prior to the Dual I/O Fast Read command.Dual I/O Fast Read With “Continuous Read Mode”

The Dual I/O Fast Read command can further reduce command overhead through setting the “Continuous Read Mode” bits(M7-0) after the input 3-byte address (A23-A0). If the “Continuous Read Mode” bits (M7-0) =AXH, then the next Dual I/O FastRead command (after CS# is raised and then lowered) does not require the BBH command code. The command sequence

is shown in followed Figure11. If the “Continuous Read Mode” bits (M7-0) are any value other than AXH, the next commandrequires the first BBH command code, thus returning to normal operation. A “Continuous Read Mode” Reset command canbe used to reset (M7-0) before issuing normal command.

Figure10. Dual I/O Fast Read Sequence Diagram (M7-0= 0XH or not AXH)

Figure11. Dual I/O Fast Read Sequence Diagram (M7-0= AXH)

Quad I/O Fast Read (EBH)

The Quad I/O Fast Read command is similar to the Dual I/O Fast Read command but with the capability to input the 3-byteaddress (A23-0) and a “Continuous Read Mode” byte and 4-dummy clock 4-bit per clock by IO0, IO1, IO3, IO4, each bit beinglatched in during the rising edge of SCLK, then the memory contents are shifted out 4-bit per clock cycle from IO0, IO1, IO2,IO3. The command sequence is shown in followed Figure12. The first byte addressed can be at any location. The address isautomatically incremented to the next higher address after each byte of data is shifted out. The Quad Enable bit (QE) ofStatus Register (S9) must be set to enable for the Quad I/O Fast read command. To ensure optimum performance the HighPerformance Mode (HPM) command (A3H) must be executed once, prior to the Quad I/O Fast Read command. Quad I/OFast Read With “Continuous Read Mode”

The Quad I/O Fast Read command can further reduce command overhead through setting the “Continuous Read Mode” bits(M7-0) after the input 3-byte address (A23-A0). If the “Continuous Read Mode” bits (M7-0) =AXH, then the next Quad I/O FastRead command (after CS# is raised and then lowered) does not require the EBH command code. The command sequenceis shown in followed Figure13. If the “Continuous Read Mode” bits (M7-0) are any value other than AXH, the next commandrequires the first EBH command code, thus returning to normal operation. A “Continuous Read Mode” Reset command canbe used to reset (M7-0) before issuing normal command.

Figure12. Quad I/O Fast Read Sequence Diagram (M7-0= 0XH or not AXH)

Figure13. Quad I/O Fast Read Sequence Diagram (M7-0= AXH)

Quad I/O Word Fast Read (E7H)

The Quad I/O Word Fast Read command is similar to the Quad I/O Fast Read command except that the lowest address bit(A0) must equal 0 and only 2-dummy clock. The command sequence is shown in followed Figure14. The first byte addressedcan be at any location. The address is automatically incremented to the next higher address after each byte of data is shiftedout. The Quad Enable bit (QE) of Status Register (S9) must be set to enable for the Quad I/O Word Fast read command. Toensure optimum performance the High Performance Mode (HPM) command (A3h) must be executed once, prior to the QuadI/O Word Fast Read command.

Quad I/O Word Fast Read With “Continuous Read Mode”

The Quad I/O Word Fast Read command can further reduce command overhead through setting the “Continuous ReadMode” bits (M7-0) after the input 3-byte address (A23-A0). If the “Continuous Read Mode” bits (M7-0) =AXH, then the nextQuad I/O Word Fast Read command (after CS# is raised and then lowered) does not require the E7H command code. Thecommand sequence is shown in followed Figure15. If the “Continuous Read Mode” bits (M7-0) are any value other thanAXH, the next command requires the first E7H command code, thus returning to normal operation. A “Continuous ReadMode” Reset command can be used to reset (M7-0) before issuing normal command.Figure14. Quad I/O Word Fast Read Sequence Diagram (M7-0= 0XH or not AXH)

Figure15. Quad I/O Word Fast Read Sequence Diagram (M7-0= AXH)

Page Program (PP) (02H)

The Page Program (PP) command is for programming the memory. A Write Enable (WREN) command must previously havebeen executed to set the Write Enable Latch (WEL) bit before sending the Page Program command.

The Page Program (PP) command is entered by driving CS# Low, followed by the command code, three address bytes andat least one data byte on SI. If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data that goes

beyond the end of the current page are programmed from the start address of the same page (from the address whose 8 leastsignificant bits (A7-A0) are all zero). CS# must be driven low for the entire duration of the sequence. The Page Program

command sequence: CS# goes low → sending Page Program command → 3-byte address on SI → at least 1 byte data on SI→ CS# goes high. The command sequence is shown in Figure16. If more than 256 bytes are sent to the device, previouslylatched data are discarded and the last 256 data bytes are guaranteed to be programmed correctly within the same page. Ifless than 256 data bytes are sent to device, they are correctly programmed at the requested addresses without having anyeffects on the other bytes of the same page. CS# must be driven high after the eighth bit of the last data byte has beenlatched in; otherwise the Page Program (PP) command is not executed.

As soon as CS# is driven high, the self-timed Page Program cycle (whose duration is t PP) is initiated. While the Page

Program cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The WriteIn Progress (WIP) bit is 1 during the self-timed Page Program cycle, and is 0 when it is completed. At some unspecified timebefore the cycle is completed, the Write Enable Latch (WEL) bit is reset.

A Page Program (PP) command applied to a page which is protected by the Block Protect (BP4, BP3, BP2, BP1, BP0) is notexecuted.

Figure16. Page Program Sequence Diagram